Core engineering and protocols for Line-Rate Bus Encryption.
Serial Peripheral Interface (SPI) buses run at high clock frequencies (33 to 50 MHz). Software-based bus encryption would introduce unacceptable latency delays during BIOS execution. TPMShield embeds dedicated pipelined AES-CCM hardware blocks directly into the TPM interface and host chipset, streaming encrypted data bits with under 40 nanoseconds of pipeline latency.
In addition to confidentiality, TPMShield validates cryptographic Message Authentication Codes (MAC) on every frame. If an attacker injects voltage glitches or manipulates bus bits to alter TPM command opcodes, the hardware MAC verification fails immediately, aborting the transaction and asserting a security interrupt.